1. Field of the Invention
Embodiments of the present invention relate to a memory system using a simultaneous bidirectional input/output (SBD I/O) circuit on an address bus line. This application claims the priority of Korean Patent Application No. 2004-13010, filed on Feb. 26, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
As operating speeds and computing power of processors develop, in some applications, the processors' computing capacity exceeds the speed at which data can be transmitted from peripheral devices to the processors. Limitations of the data rate between the processors and peripheral devices (i.e. limitations of data bandwidth) may result in operational limitations of the processor system. A data bandwidth of a processor system may be increased by increasing a size of a data bus. In a personal computer (PC) system, a data bus may have 8-, 16-, 32-, 64-, and 128-bit widths, periodically doubling. Other applications may mitigate data bandwidth problems by using a larger data bus. For example, in a parallel computing system, a plurality of parallel processors use data buses which are several hundreds of bits in width. Extension of a data bus width is limited by physical requirements of integrated circuits (ICs) connected to the data bus. ICs may be packed into a package and connected to a bus line through package pins. Packages may not have enough pins to be connected to hundreds of bus lines of a system, because of practical limitations on the size of the packages.
An SBD I/O circuit is used to increase a data bandwidth, without increasing bus size. In a system using the SBD I/O circuit, data transmission and data reception are simultaneously performed through a single data line, which effectively doubles the data bandwidth without physically increasing the bus size. Such a SBD I/O circuit is disclosed in U.S. Pat. No. 6,127,849. The SBD I/O circuit is present between data bus lines and performs simultaneous bi-directional data transmission. FIG. 1 illustrates a memory system using the SBD I/O circuit.
Referring to FIG. 1, a memory system 100 includes a memory controller 110 and a memory device 120 (e.g. a dynamic random access memory (DRAM)). The memory controller 110 and the memory device 120 are usually connected via an address bus line CA and a data bus line DATA. The data bus line DATA is connected between a data I/O circuit 112 of the controller 110 and a data I/O circuit 122 of the memory device 120. The data I/O circuits 112 and 122 constitute the SBD I/O circuit so that data is transmitted in two directions from the controller 110 to the memory device 120 and from the memory device 120 to the controller 110.
The address bus line CA is connected between a command address output buffer 114 of the controller 110 and a command address input buffer 124 of the memory device 120 so that a command address output from the controller 110 is input into the memory device 120. In other words, the command address is transmitted in a single direction from the controller 110 to the memory device 120.
As memory systems develop to operate at faster operating speeds, the command address is transmitted at a relatively fast rate, and as a result, errors in the transmitted command address are more likely to occur.